Design & Verification

VLSI Verification (UVM)

Functional verification from basics to industry-level UVM with protocol and advanced projects.

Hybrid Intermediate
Overview
A complete VLSI Verification program that takes you from digital fundamentals and Linux scripting to SystemVerilog and UVM. You will build reusable testbenches, practice coverage and assertions, and complete protocol and industry-style projects to become job-ready for DV roles.
Key features
This page focuses on highlights and outcomes (no price shown).
Design & Verification
Functional Verification from basics to industry-level UVM Protocol verification projects + advanced industry projects Coverage-driven verification and assertion-based verification Tool exposure and waveform debug workflows Interview preparation with project story building
Syllabus
Modules are editable in Admin.

  • Binary system, logic levels, noise margins
  • Combinational circuits: Adder, Subtractor, MUX, Decoder, Encoder
  • Sequential circuits: Flip-flops, Latches, Counters, Shift Registers
  • Finite State Machines (Mealy & Moore)
  • Timing concepts: Setup time, Hold time, Clock domains

  • Linux commands and file system
  • Bash scripting fundamentals
  • Perl / TCL automation
  • SED, AWK and regular expressions
  • Environment variables and shell programming

  • Gate primitives and continuous assignments
  • Structural, dataflow and behavioral modeling
  • RTL coding practices
  • Tasks, functions and compiler directives

  • Advanced data types and interfaces
  • Object oriented programming concepts
  • Constrained random verification
  • Functional coverage
  • SystemVerilog assertions

  • UVM components and factory
  • UVM phases
  • Sequences and drivers
  • Transaction level modeling
  • Configuration database and reporting

  • Directed testing vs constrained random testing
  • Coverage driven verification
  • Assertion based verification
  • Formal verification basics
  • Clock domain crossing and low power verification

  • I2C verification
  • AMBA APB verification
  • AMBA AHB verification
  • AMBA AXI verification
  • Synchronous and asynchronous FIFO verification
  • Dual port RAM verification

  • DDR5 Memory Controller Verification
  • PCIe Gen6 Verification
  • AXI Interconnect Verification
  • Ethernet MAC Verification
  • NoC verification

  • Synopsys VCS
  • Cadence Xcelium
  • Mentor QuestaSim
  • SpyGlass linting
  • JasperGold formal verification
  • DVE / SimVision waveform viewers

  • Verification Engineer
  • ASIC Design Verification Engineer
  • SoC Verification Engineer
  • Verification Architect
  • DV Manager
Outcomes
Build strong fundamentals in Verilog and SystemVerilog for verification
Create reusable UVM testbenches with sequences, drivers, monitors and scoreboards
Apply constrained-random testing, assertions and coverage-driven verification
Complete protocol and industry-style verification projects for interviews
Next Batch
Featured
Admissions Open
Limited seats
UVM from basics to industry-level
Hands-on labs + verification projects
Coverage + assertions + debug mindset
Mock interviews + career guidance
SystemVerilog: OOP, coverage, assertions
UVM: phases, factory, sequences, config DB
Protocol projects: I2C / APB / AHB / AXI
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